1. Field of the Invention
The present invention relates generally to bipolar transistors, specifically, heterojunction bipolar transistors, and, more particularly, to methods for reducing the base-collector junction parasitic capacitance of such transistors.
2. Description of Related Art
In a heterojunction bipolar transistor (HBT) device mesa structure, the intrinsic region of the device is determined by the emitter geometry. The transistor action in the intrinsic region of the device takes place in a volume directly under the emitter contact. The base-emitter (B-E) junction area, which is defined by mesa etching down to the base surface, determines the lateral cross-section of the intrinsic device. However, for contacting to the base terminal, the base mesa, which defines the base-collector (BC) junction area, is made larger than the B-E junction area, often over twice as large. Making the B-C junction area substantially larger than the B-E junction area leads to a large extrinsic B-C capacitance C.sub.BC, which is undesirable.
A number of attempts have been made to correct this problem. In one approach to solve the problem, buried-implant damage is used to reduce the extrinsic portion of the C.sub.BC ; see, e.g., Mau-Chung F. Chang et al, "AlGaAs/GaAs Heterojunction Bipolar Transistors Fabricated Using a Self-Aligned Dual-Lift-Off Process", IEEE Electron Device Letters, Vol. EDL-8, No. 7, pp. 303-305 (July 1987). In the case of GaAlAs/GaAs HBTs, the buried ion-implantation technique neutralizes the parasitic portion of the CBC (i.e., the area of the junction which is not directly under the emitter). In this approach, oxygen or boron is used to damage the GaAs collector region contributing to the parasitic portion of the C.sub.BC.
However, in the case of a GainAs collector used in AlInAs/GaInAs HBT devices, no ion-implant procedure exists that can adequately damage GainAs and thus reduce the extrinsic portion of the C.sub.BC. Therefore, this procedure is not applicable to AlInAs/GaInAs HBTs.
In general, the buried ion-implant procedure is also costly because of the need for an ion implanter and it is complicated because it requires extensive development. Furthermore, even in the case of GaAs-based HBTs where buried implantation damage is possible, there are a number of drawbacks to this technique. This process requires an elaborate ion-implantation facility and process. In addition, it results in a number of adverse side effects, including severe reduction in the current gain as well as potential long-term reliability problems for the devices.
In another approach to solve the problem, dry-etching techniques are employed; see, e.g., T. R. Followan et al, "High Yield Scalable Dry Etch Process for Indium Based Heterojunction Bipolar Transistors", Proceedings of InP and Related Materials Conference, WP15, pp. 343-346 (1992). However, there are several drawbacks to using dry-etching in attempt to reduce the extrinsic portion of the C.sub.BC. Cost and complexity of the process is one major drawback. Second, it is generally difficult to use photoresist as a mask for dry-etching of GainAs. Third, the mask that is used to etch the GainAs is not suitable for lift-off of the evaporated oxide because it does not have the proper profile for lift-off. Even if the lift-off was possible, there will be a gap formed between the back-filled oxide and the mesa which will cause a short between the base and collector when base metal runs over it. Therefore, a second masking step is required to do the oxide evaporation and lift-off, however, the second masking step is an extra processing step and is not "self-aligned" to the etched mesa. Therefore, it requires the usual alignment tolerances which results in a larger mask. A larger mask increases the extrinsic base-collector area, and thus, increases the C.sub.BC.
Thus, there remains a need for a process of reducing the base-collector capacitance in heterojunction bipolar transistors that does not suffer from the disadvantages of the prior art approaches.